TweakTown
Tech content trusted by users in North America and around the world
6,159 Reviews & Articles | 39,584 News Posts
TRENDING NOW: Star Citizen creator: "I don't care about consoles"

TSMC and Cadence Strengthen Collaboration on 16 nm FinFET Process Development

Cadence Design Systems, Inc., today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs -- from design analysis through signoff -- and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.

 

TweakTown image pr/8/1/8160_01_tsmc_and_cadence_strengthen_collaboration_on_16_nm_finfet_process_development.jpg

 

FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16 nanometers and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.

 

"The FinFET device requires greater accuracy, from analysis through signoff, and that is why TSMC is teaming with Cadence on this project," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "This collaboration will enable designers to use the new process technology with confidence earlier than ever before, allowing our mutual customers to meet their power, performance and time-to-market goals."

 

"Producing the design infrastructure necessary for these types of complex, groundbreaking processes requires close collaboration between foundries and EDA technology innovators," said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "In joining with TSMC, a leader in FinFET technology, Cadence brings unique technology innovations and expertise that will provide designers with the FinFET design capabilities they need to bring high-performance, power-efficient products to market."

Related Tags

Further Reading: Read and find more Business, Financial & Legal press releases at our Business, Financial & Legal PR index page.

Do you get our RSS feed? Get It!

Got an opinion? Post a comment below!

Latest Tech News Posts

View More News Posts

Forum Activity

View More Forum Posts

Press Releases

View More Press Releases