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AMD has announced a new line of APUs for use in embedded applications. The new APUs are the first to combine a low-power CPU and a discrete-level GPU into a single integrated circuit for use in embedded applications. The high performance graphics capabilities allow the APU to power a wide array of devices such as slot machines and airline schedule screens.
AMD bills the part as being perfect for Digital Signage, x86 Set-Top-Box (xSTB), IP-TV, Thin Client, Information Kiosk, Point-of-Sale, and Casino Gaming, media servers and industrial control systems. The APU comes in a BGA package featuring a new, power-optimized CPU processing core to provide more bang for the user's buck.
The features are as follows:
- DirectX® 11 support lets you enjoy awesome graphics performance, stunning 3D visual effects and dynamic interactivity.
- Advanced discrete-level GPU with OpenGL 4.0 and OpenCL 1.1 support in an integrated device provides support to build the designs of tomorrow, today.
- Unprecedented graphics performance/watt thru advanced graphics and hardware acceleration delivering over 3X performance per watt of previous generation.
- Selective models, T56N and T40N, have additional boost capability enabled by AMD Turbo Core technology without additional power draw.
There's still a fair bit of time before Intel releases server chips based upon the Ivy Bridge architecture, but that isn't stopping avid readers and power users from questioning what comes next. Next, by the way, is Haswell, which is the successor to the current Ivy Bridge architecture and is a completely new design.
The leaked slides would appear to be real and detail some of the chip's features that we should expect when it releases. As far out as it still is, some of these details could be subject to change. The slide claims that there will be minimum of 10 cores per CPU and will sport up to 35MB of total LLC, about 2.5MB a core.
It is said to have 40 PCI-e lanes and will sport Hyperthreading and Turbo Boost. It appears that the new CPU will be getting a new socket (of course) called R3 or Socket R3. This is most likely so that it can handle the 4 channels of DDR4 operating from 1333MTS all the way up to 2133MTS. Additionally, it sports two QPI paths so there will be a max of two CPUs per system.
Intel DDR4 servers are supposed to debut in 2014, so don't be expecting Haswell-EP before then. That puts 2014 as the most probable time for when Haswell-EP will shed its NDA and more information will come available.
Toshiba have just made quite the leap, announcing they have developed a low-power, 64-core System-on-a-Chip (SoC) for embedded application in some areas which could be destined to automotive products and digital consumer products.
The insane chip sports 64 cores, claiming to feature eight times as many as its multi-core predecessor unveiled in 2008 and operates at an insane 14 times faster. The 64-core chip sits on a die area of 209.3mm2, two 32-core clusters are then integrated with dynamically reconfigurable processors, hardware accelerators, dual-channel DDR3 memory controller and other peripherals.
In one cluster, we'll find processor cores that share 2MB of L2 cache connected through a three-based network-on-chip (NoC). The high scalability and low power consumption is accomplished by the parallelized firmware for multimedia applications.
Take a quick stroll down memory lane and find Larrabee. Larrabee was Intel's failed discrete graphics creation designed to go head-to-head with the likes of NVIDIA and AMD. The Larrabee project was canned but Intel decided to continue the work with a change of focus. Instead of being a discrete GPU, Intel decided to target the HPC and supercomputing markets.
This new chip is an in-development chip known as Knight's Corner and is designed to be massively parallel. The product has clearly made significant progress as Intel has officially attached a brand name to the product. That brand name is Xeon Phi and will also be attached to future many-integrated-core (MIC) products.
Intel chose Xeon Phi as they wanted it to be part of the Xeon family. As for the Phi part, Intel says it's because it "evokes many concepts in science & nature including the 'golden ratio' in mathematics." Along with the brand name, Intel has released some technical details of the upcoming MIC chip.
The chip will be in production "in 2012" and be fabricated on Intel's 22nm process. The chip will feature more than 50 cores and "8GB+ GDDR5 memory" on a PCI Express card interface. Intel has asserted that the chip is capable of 1+ teraflops of double-precision compute throughput in Linpack. Intel has built a Knight's Corner cluster capable of producing 118 tflops as a proof-of-concept.
AMD's Mark Papermaster, senior vice president and chief technology officer of AMD, has said that they will be making a major change to its manufacturing process in 2013. AMD is planning on switching from its current SOI process to a 28nm Bulk CMOS process for the 2013 line of products. This, however, should not affect GPU manufacturing.
The current 7000 series "Southern Islands" GPUs currently makes use of TSMC's 28nm process. The upcoming "Sea Islands" GPUs will continue to make use of TSMC's 28nm process. The Sea Islands GPUs have already entered tape-out and should begin being manufactured in the end of 2012. The product should release first quarter of 2013.
Additionally, Papermaster pointed out that AMD is not opposed to working with other manufacturing houses as long as they benefit AMD in product launches. Papermaster furthermore commented that the HSA foundation was not directed at any specific competitor and ARM and AMD are only working together to combine ARM's TrustZone into AMD's APUs.
At the end of the Fusion Developer Summit, Mark Papermaster, AMD Executive VP and CTO, produced some roadmaps which provided us a small glimpse into the future plans of AMD. AMD is looking to bring three new APUs to market in 2013 and 3 new server chips later this year. With the come new updated core architectures.
Let's start with the APUs. AMD is planning 3 different versions for various markets. The top APU is codenamed 'Kaveri' and will feature 4 Steamroller cores. Steamroller is the successor to the Bulldozer/Piledriver cores. This APU will feature fully shared memory with the GPU and have 15-35W thermal envelopes and be used in 13.3-15.6" notebooks with thicknesses of 0.83" or less.
The middle APU is codenamed 'Kabini' and will be the successor to the Zacate and Ontario APUs. The Kabini APU will sport Jaguar cores which are the next iteration of the Bobcat core architecture. Thermals will be in the 9-25W range and be used in 11.6-15.6" notebooks with thicknesses in the neighborhood of 0.71-0.94". The bottom APU, 'Temash,' will be similar and manage to fit into a thermal envelope of 3.6W. Wow.
DigiTimes is reporting that Intel are to begin the phasing out of their Sandy Bridge-based processors this September. This paves the way for Ivy Bridge to get slapped into various products such as the Ultrabooks Intel are pushing big time.
Intel have said that OEMs have already begun receiving shipments of Ivy Bridge CPUs, with customers starting to notice them in systems later this month. Intel have also hinted that they expect to ship some 50-percent more Ivy Bridge CPUs in six months that it did in the same time period with Sandy Bridge.
But, there is a but here, folks. Ivy Bridge-based CPUs are much more expensive than their Sandy Bridge counterparts. According to DigiTimes, the price disparity is around $67-$100 per unit. This is a big problem for OEMs who are working on razor-thin margins on mainstream products that are the norm. If the Sandy Bridge chips do start disappearing in September, we should expect price cuts sometime this summer.
AMD has announced some more details on its upcoming Trinity APUs destined for desktops. AMD has stated that these chips will start to appear in all-in-one PCs by the end of the month. Curiously, this is contrary to what several motherboard manufacturers told TechReport while at Computex. They had said that desktop parts were delayed.
It looks as though AMD may be respinning the silicon for the retail desktop chips, so it probably won't be identical to the chips OEMs will be receiving this month. That aside, we do know the models which will be becoming available this month. The chips are almost identical to the mobile chips, except that they will be clocked higher.
All of the CPUs feature a quad-core CPU based upon the new Piledriver architecture and 4MB of L2 cache. They will support up to DDR3 at 1866MHz and slip into the FM2 socket. The K series denotes chips that are unlocked for overclockers, so if you plan to overclock, make sure to pay attention and get the correct model.
Computex 2012 - Overclocking is a huge thing here in Computex, where at the G.Skill booth they had some of the world's best overclocking champions facing it off on-stage. Young Pro, Hiwa, and Fred Yama were all there as we walked past.
If you remember, G.Skill are having their world-class overclocking invitational, and these great OC champs were going head-to-head. The presence and aura there was great, the crowd was loving it and the G.Skill booth babes were some of the best there. Yellow and black looks awesome, doesn't it?
Ahead of Computex next week, Intel have released details on 14 new dual-core Ivy Bridge-based processors. Core i5 and i7 processors will be among the first to drop, with Core i3 variants arriving later this year.
The Core i3 processors will also be joined with new Pentiums and Celerons, too. Out of the 14 new dual-core processors, six of them are desktop-grade, which means the remaining 8 of them are destined to mobile and ultra-low voltage. Ultra-low voltage chips sport a "U" in their name, which gives their identity away.
With Computex happening next week, we should expect to see a slew of Ultrabooks sporting the new ultra-low voltage Core processors. We should have a bunch of hands-on talk with various models, chips, Ultrabooks and so forth, so check back each and everyday next week for our coverage of Computex!