Following the recent unveiling of their next-gen Phenom (K10) desktop parts earlier in the week, AMD have revealed some more information to the masses about their upcoming "Puma" platform and dual-core 65nm "Griffin" processor range for the notebook market.

Set to take on Intel Centrino, it is reported that AMD plan to focus much of their attention on superior power saving technology, it will be capable of scaling down to 1/8th of its rated clock speed which is quite a massive drop when the extra power isnt needed. Split power planes will be used for the processor cores and memory controller , meaning it will be theoretically possible to disable one core for further conservation of power.

Some other features are HyperTransport 3.0 support, 802.11n Wi-Fi standard, Hybrid hard disk, DirectX 10 graphics and PCI Express 2.0 support. It is said we wont see the platform released for a good while yet though, they appear to be aiming for a late 07 / early 08 launch.

There's some coverage floating around on the web with more information about it at the following sites :-

- Dailytech
- Anandtech
- Hot Hardware
- bit-tech
- XBit Labs

AMD is preparing to take on Intel's Centrino, current Santa Rosa and upcoming Montevina, platforms with the next-generation Puma mobile platform. At the heart of Puma is AMD's next-generation Griffin-core 65nm mobile processor, ready to take on Intel's Core 2 Duo with a power saving vengeance. Griffin is a dual-core mobile processor geared towards enhanced performance without sacrificing battery life.

AMD's Griffin features extensive power saving characteristics, more so than its upcoming Barcelona-family, such as an improved split power plane. The split power plane supported by Griffin allows the memory controller and each processor core to operate with independent voltages. Griffin's DDR2 memory controller also features an improved DRAM pre-fetcher and enhancements in efficiency. With the split power planes, the memory controller's power plane operates at a lower voltage than the two CPU cores.