- AMD Athlon 64 Processors on E3 Core: Memory Controller Peculiarities in Detail
It's been known for quite a while now that up until the recently introduced "E" core revision Athlon64 CPUs from AMD (Venice/San Diego/X2), earlier revision processors had a rather fragile in-built memory controller in terms of throwing uneven memory modules at it and/or more than 2 sticks at a time. Supposedly the new and improved memory controller found in all the latest revision A64 chips will eliminate these earlier issues, as well as adding DDR500 SDRAM support to boot. XBit Labs decided to put it to the test and see if this holds true, along with an extensive analysis behind what memory modules/configuration plays best with regard to performance and stability levels. A very interesting readup!
Not so long ago AMD64 processor family with new E core revision appeared in the market. This processor core manufactured with 90nm process using SOI (Silicon on Insulator) and DSL (Dual Stress Liner) technologies got into a few processor product lines. The new E core found its way into several application fields. You can see it in Athlon 64 and Athlon 64 FX processors, where it is known under Venice and San Diego code names, as well as in dual-core Athlon 64 X2 processors, where it is known as Toledo or Manchester. It is also used in AMD Sempron processors where they call it Palermo.
When AMD develops and puts into mass production new processor cores, it aims not only at increasing the working frequencies of their new processors based on these cores, but also at improving their features and specifications. The E core revision appeared another threshold on this way: it provided Athlon 64 processors and their modifications with a number of absolutely new features. One of the most significant enhancements appeared the support of new SSE3 instructions, which has been already implemented in the competitor's solutions since the 90nm Prescott core. Moreover, the integrated memory controller also underwent a few noticeable enhancements.
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