The introduction of newer, smaller flash geometries will require sophisticated error correction ability to maximize endurance of the NAND. As NAND matures, it almost seems counter-intuitive that we will lose endurance as NAND shrinks, but economics have a hand in the smaller NAND geometries. In order to provide a more economical and accessible product through shrinks, endurance suffers as a trade-off.
One of LSI's core competencies has always been strong ECC techniques, which originated with their extensive hard drive controller experience. The addition of these new LSI SHIELD error correction technologies shows a sign of some of the mutual benefits from the LSI/SandForce acquisition.
Enabling advanced Low-Density Parity Check (LDPC) allows LSI SandForce to create a stable solution that will mesh well with not only lower endurance MLC and TLC, but will also wring extra endurance out of current generation NAND as well. This is accomplished through a variety of techniques, including an adaptive method of adjusting the level of ECC during the life of the SSD.
This uses lighter error correction in the early stages of NAND life, and increases the intensity of ECC as the NAND ages and begins to generate more errors.
The Adaptive Code Rate also requires less ECC data affixed to each NAND page, returning some capacity of the SSD to the controller. In tandem with the new DuraWrite DVC (DuraWrite Virtual Capacity) technology, this extends this extra capacity into the hands of the user.