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PCI-Express 3.0 - nearly finished being an unsolved mystery

PCI-Express 2.0 has been here for us for what seems like an eternity in the tech world - so much mov

| Motherboards News | Posted: Nov 27, 2010 1:00 pm

PCI-Express 2.0 has been here for us for what seems like an eternity in the tech world - so much moving past us in terms of cores on a CPU, the amount of system ram and at the moment the apocolyptic GPU wars between the great AMD and NVIDIA.

 

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PCI-Express 3.0 is the next gen champion to be on your motherboard. It is rumored to be clashing it's hammer with the Sandy Bridge E 'Patsburg' on LGA2011 which is slated for 2011. Depending on whether the LGA2011 becomes the consumer-targetted replacement. The closest definite for PCI-Express 3.0 is for early 2012 when Ivy Bridge hits.

 

What will it bring us you say? We see a doubling in speed from PCI-Express 2.0's bandwidth of 4Gbps to a next-gen of 8Gbps, a 100% increase - also remember that is per lane in each direction which means the total bandwidth going to the next gen is going to be 32Gbps. This gives it a huge upgrade to allow GPU's to start running laps around their current high end VGA cards.

 

In order to get a doubling in speed from the current PCI-Express 2.0 standard - PCI-SIG (the guys behind the spec) have also lessened the encoding overheads to make faster transfers even more efficient.

 

It's kryptonite? Currently signalling bus devices (like PCI-Express 2.0) use an '8b/10b' encoding - which means ten bits are transferred for eight bits (one byte) of actual data. Obviously this isn't optimal, 10bits used for only 8bits of actual data - which is quite a considerable amount (20 percent). To get out of this issue PCI-Express 3.0 encodes the data in a much larger amount, a 128b/130b amount to be exact.

 

Following that is 'a known polynomial is applied to a data stream in a feedback topology', with an 'inverse polynomial' sat at the other end to decode the data. In non-nerd speek it's a hardcoded mathematical function that is designed more efficiency for the handling of 0s and 1s - so they don't interfere with each other when transferred. The technique is called 'scrambling'.

 

The results of this are instead of 5GT/sec of PCI-e 2.0 increasing to 10GT/sec, PCI-Express will only require an 8GT/sec transfer - as the data is also transferring at a great efficiency (think a long drive uses less petrol in a car, then running it around town constantly). This result also uses less power - as it doesn't have to involve higher grade materials, in turn making the product cheaper to make. It's pure genius.

 

While this is both good and bad news - PCI-Express 3.0 provides not much more power than it's predecessor, but this isn't necessarily a bad thing. Having >300W drawn from each PCI-E 3.0 port is expensive to make, it would increase the thickness of copper traces on the motherboard. Manufactures such as Asus and Gigabyte could possibly need to add extra layers to try and route the high power traces and their associated electromagnetic interference away from sensitive data traces.

 

Sounds complicated? Well, it means that with greater effiency, comes less power consumption. In a world of GPU's getting to boiling point at a stated 2xxW part, where it and many others reach 300W quite easily - it's a step in a better direction.

 

NEWS SOURCES:Bit-tech.net

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