The ArchitecturesFirst off let’s take a look at the two competing architectures.
The Sempron 64 derives from the original Hammer architecture that AMD introduced back in 2003 at Computex. The Hammer architecture has slowly progressed with changes in each new core revision but the basics remain the same.
64-bit Instruction Set: We’ll start with the most important part of a modern CPU, its support for 64-bit OS’s and applications. AMD was the first to introduce a 64-bit CPU using the x86 architecture for both desktop and workstations. While supporting 64-bit registers, AMD also keeps legacy support alive by including 32-bit ISA registers. What this means to users is you can run either Windows XP 32-bit or Windows XP 64-bit, there is no limitation on this part. When running Windows XP 64-bit, you have the ability to address memory ranges above 4GB, in fact up to and beyond 16GB is possible.
Integrated Memory Controller: AMD K8 architecture is the first desktop CPU to integrate a memory controller directly to the die. AMD uses a crossbar to connect a single DDR memory channel directly to the CPU die, allowing almost instantaneous access between the L2 cache and the system memory. This results in lower latencies than a CPU accessing the system memory along a traditional FSB arrangement.
SSE3 Instructions: SSE3 was introduced by Intel in order to increase the multimedia encode and decode of the Pentium 4 based CPU’s. Since then it has now been added to AMD’s latest CPU’s to give AMD that extra advantage in applications that make use of these new instructions such as media encoding tasks.
90nm Fab process: The Sempron uses AMD’s latest 90nm Silicon on Insulator process or SOI as its known. This process has been the success for AMD in the battle of performance per watt. AMD has been able to keep temperatures down using the same 90mn die size compared to that of the 90nm Intel CPU’s.
Cache Cut: AMD Sempron 64 reduces the amount of L2 cache that is used on the CPU die. Athlon 64 based CPU’s use either 512KB or 1MB of on die L2 cache. Sempron only supports 256K L2 cache onboard. This results in a slightly slower CPU clock for clock.
HyperTransport Technology: AMD first brought out HyperTransport technology back when Athlon was Socket A. With the advent of an on-die memory controller and basic Northbridge, AMD has decided to use Hypertransport to connect the K8 architecture CPU’s to external chips.
Intel Celeron-D goes a different way from the AMD side of things with its line of CPU.
Netburst Architecture: Netburst has been the base of Intel Pentium 4 CPU’s since its introduction. Netburst uses an extremely long pipeline with double speed ALU’s. While this allows Intel to increase the speed of its CPU on a MHz race, keeping the pipeline full is a hard job and results in less work being done per clock cycle. Celeron-D uses a 133MHz Quad Pumped bus (533MHz) that connects the CPU to its Northbridge.
EM64T: While not named AMD64, Extended Memory 64 Technology (EM64T) is a direct copy of the AMD64 instruction set. Intel introduced this into its Pentium 4 600 series CPU, and has now filtered down to the Celeron-D range for the budget line. Celeron-D CPU’s with a 1 or a 6 at the end of its identification number indicate its support for 64-bit instructions (331 and 336 are 64-bit compatible).
SSE3: Celeron-D CPU’s are based on the Prescott core design, with this comes the longer pipeline and the SSE3 instruction sets. These are introduced to give the Netburst architecture a leap when it comes to heavy media encoding
90nm Strained Silicon: Rather than follow AMD down the SOI road, Intel decided to go Strained Silicon. This technology for its 90nm has been somewhat controversial due to its high voltage leak capacity as well as the extreme heat 90nm Intel CPU’s generate on a performance per watt basis.
Cache Rise: Since the Celeron introduction, all Celeron CPU’s have had a 128K L2 cache. Celeron-D increases this to 256K L2 cache. This is the highest cache level any Celeron CPU has experienced.
As you can see, there is quite a difference in architectures.
