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Intel Skylake Microarchitecture - High Level Info from IDF 2015

By: Steven Bassiri | Intel CPUs in CPUs, Chipsets & SoCs | Posted: Aug 24, 2015 1:15 pm

Power Optimizations

 

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Intel's Speed Shift Technology is aimed at optimizing how the CPU responds to workloads. Intel uses the "Race to Halt" theory to allow the CPU to work at the most optimized levels then go back down to a virtual zero energy draw state over and over again. Intel's Speed Step Technology (EIST) was also added to the System Agent, DDR, and eDRAM IO. During the questions and answers segment at the end of the technical session, it was revealed that you need Windows 10 for this technology to work, but that they were also working on Linux support.

 

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The Skylake SoC seen above shows all the different domains and how they are connected, and on the right it shows where power gating takes place.

 

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Power gating has also been added to many domains of the CPU. Even Intel's AVX2 hardware can be power gated when it is not in use. Idle power reduction was also used to lower minimum power usage. Intel went really far to power gate I/Os, PLLs, and even interconnects. Even the Intel PCH can be throttled.

 

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On the left is legacy P-state control and on the right is Speed Shift control. Green represents software control (and hardware control as well), and for the new CPU the hardware and software work together almost all the time to work out the best power state. This hand in hand software and hardware communication allows for the power savings that Skylake brings to the table.

 

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On the left is a visualization of general compute power. On the right is the SoC duty cycling for low power small form factors. The system will then go to the low power most efficient state from the graph (Pe) on the left and then back down to C6 state. This basically makes the system turn on and work and then turn off and sleep.

 

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For a technology like Speed Shift to work, you need real time sensing of hardware, as well as real time knowledge of workload demands. Intel has implemented a balancer to help determine the best frequency and power profiles to apply to the CPU at any given time. It uses a PID controller, similar to what we see in modern digital PWMs for balancing inputs and real-time sensing of the output.

 

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I decided to include some of these interesting slides as well on the benefits of using the new power algorithms and OS control over the legacy hodgepodge of P states.

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