DDR-2 in Detail
Prepare yourself as we will be going into the heart of DDR-2 technology here.
DDR-2 technology is a direct extension of the already popular and mature DDR technology. In fact, the reason DDR-2 and DDR is almost identically compatible and require minimal reconfigurations of the DRAM controllers is that is has the identical same command structure, just a slightly different way of going about its processing of the data. What does this all mean? Well let's have a look at the DDR-2 architecture and how it actually works compared to the DDR technology.
DDR SDRAM uses a simple premise - it takes the existing command issue structure and DQ (or Data Queue) and allows the array to send two bits of data per clock cycle rather than the standard one of SDR. This is done by using both the rising and falling edges of the clock cycles, effectively allowing you to send twice the data at the same bus frequency. This is how DDR was able to get 200MHz rating while still using a 100MHz bus speed.
DDR-2 uses the exact same sending technique, two bits per clock cycle, however, the internal memory cell array and buffers have been changed.
Here we see how DDR-2 allows a much broader range of data to be sent which is achieved by effectively a dual core system. Two cores are added to the cell array allowing both to operate independently; each core has the two bit system, which doubles this to four bits total. The data buffer in order to allow both the cores to operate at their peak runs at twice the speed of the cell array, allowing each array to dump its memory into the buffer for the trip along this bus. While the bus remains at the same speed, this new architecture works something like the Intel Quad Data Rate bus in order to give 4 times the speed of the internal clock. DDR at 100MHz clock has a speed of 200MHz and DDR2 at 100MHz clock is effectively 400MHz. This is how DDR-2 gets it speed increase, as it allows the clocks to be lowered while increasing the overall data throughput. With this in mind, 200MHz DDR put into a DDR-2 fashion would give us 800MHz, well beyond that of the DDR capabilities.
Added to this is the major issue of the maximum speed obtainable today. Sure 800MHz is good but more is needed when we are looking at pushing beyond what is available today. This is where DDR-2 distinguishes itself from DDR with a few additional tricks up its sleeve. First off is the reduction in manufacturing processes, allowing for a smaller die which is able to push beyond what DDR is capable of. DDR-2 is a standard in the FBGA or Fine Ball Grid Array Package. This package is not totally dissimilar to that used by Kingmax Technology with its TinyBGA system for many of the past years and in fact, it is almost identical. This means that the units will generate less heat, and require less power. When you put a Smaller Die + Cooler running package + lower voltages you will end up with clock speeds beyond what is available in DDR modules, and should soon see 1GHz DDR-2 modules starting their testing phase with some enthusiast memory companies such as OCZ and Corsair already selling 675MHz DDR-2 modules.
DDR-2 uses a new voltage requirement that DDR just can't match. With the lower heat generation and smaller packages, the required voltage for DDR-2 has been set at an amazingly low 1.8 volts. This was achieved by replacing the single way differential strobe with a bidirectional I/O buffer strobe.
One of the most significant changes to the system is the new On Die Termination. On DDR motherboards the signal termination was handled by resistors on and around the motherboard DRAM sockets. When at the lower 266MHz and 333MHz speeds this works out quite well, however, when pushing up clock frequencies, the requirement for terminating the bus noise become a crucial one, and DDR just gets too noisy with the termination system on the motherboard itself. DDR-2 changes this by incorporating an on die resistor that connects to the main ground of the DRAM channel. This allows signal noise and reflections to be cancelled out on the actual die of the memory package. This helps as the noise from one module won't travel along to another module and cause further havoc as well as keeping the noise on the actual package to a total minimum, allowing a much cleaner signal to flow along the bus.
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