An Innovative Solution: 3D V-NAND
Samsung's answer to the NAND scaling challenge is a first in the semiconductor industry. Traditionally, memory scaling has progressed through process shrinks, but Samsung is innovating by stacking NAND cells vertically atop each other. Instead of starting at 20nm and dealing with its known issues, Samsung stepped back to 3Xnm NAND as the building block for V-NAND due to a number of advantages. 3Xnm is a proven process with good yields, and provides a stable platform for stacking cell layers.
V-NAND production begins by adding 32 layers of cells to the NAND die. Each layer adds additional cells for data storage. The next step in the manufacturing process etches over 2.5 billion channel holes from the top layer of the NAND to the bottom. This vertical interconnect process technology creates small tunnels that link each layer of NAND cells.
Structural Innovation With Charge Trap Flash
Reducing interference, Enhancing Endurance
One of the key enablers for V-NAND is the development of Charge Trap Flash (CTF). CTF combats cell-to-cell interference by temporarily storing the electric charge in a non-conductive layer of silicon nitride (SiN). Samsung modified CTF into a three-dimensional design by wrapping the control gate and Si-Channel around the non-conductive SiN (insulator). Holding the charge in an insulator layer instead of a capacitor, as in typical floating gate designs, resists failure from defects.
CTF also requires less voltage to program each cell. Higher cell-programming voltages are the primary reason for reduced endurance in smaller NAND lithographies, and V-NAND's voltage reduction results in less stress on NAND cells.
The combination of enhanced defect resistance and lower programming voltages significantly increases the endurance of the NAND cells, providing 35,000 P/E Cycles for the new 32-layer V-NAND. This is a 10X increase over the 3,000 cycles provided by planar NAND.
Stacking cell layers also doubles the density of the NAND, allowing it to hold more data in the same footprint. Lower cell programming voltages not only increases endurance, but also increases performance while reducing power consumption.
A key differentiator for V-NAND SSDs is lowered power consumption, which provides a tangible boost in efficiency in read-centric applications, and longer battery life in mobile applications. In heavy workloads, lower power consumption leads to significant operational savings, especially in data centers with arrays of SSDs in use.
The increased density offered by V-NAND allows for smaller devices with greater capacity. Packing more data per die provides greater storage space in a smaller footprint. Each individual die, with its capacity of 86Gbit, will be stacked with up to 16 more dies in a single package. This reduces the overall number of NAND packages required for data storage, and provides the added advantage of lower power
The increased performance of V-NAND results in much higher performance, particularly in lower capacity SATA SSDs. Larger capacity SSDs do not benefit as much from the increased performance due to limitations of the SATA 3 connection.
The more robust performance of V-NAND also carries over to trace-based testing. Trace-based testing emulates real-world workloads to simulate a typical user workload. These mixed workloads can be very demanding, and the resilience and superior speed of V-NAND delivers improvement over competing products.
As future M.2 and PCIe SSDs come to market the true performance of V-NAND will be unleashed through the faster interfaces. The 128GB Samsung 850 Pro, which utilizes 32-layer V-NAND, features impressive write performance that distances itself from competitors.
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- Page 1 [Introduction: The V-NAND Paradigm Shift]
- Page 2 [Scaling Challenges of Planar (2D) NAND]
- Page 3 [An Innovative Solution: 3D V-NAND]
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