Scaling Challenges of Planar (2D) NAND
The key to reducing the price per GB of flash-based products is continued process shrinks, or 'scaling'. NAND scaling packs more bits per square inch with each smaller process. Planar NAND has presented several challenges as lithography shrinks. Planar NAND cannot scale much further in length and width on the die surface, leaving process shrinks as the primary method for increasing capacity.
NAND stores data as electrons in cells constructed of floating gate transistors. Shrinking the transistors provides more storage density, and thus lower cost. Unfortunately, shrinking the floating gate reduces the number of electrons held per cell, and smaller structure geometries tend to exhibit reduced endurance due to wear and breakdown of materials.
NAND endurance is measured in P/E Cycles a measurement of the number of times each cell can be programmed and erased before the cell is worn out. 50nm NAND featured 10,000 P/E Cycles, and each newer generation of 2D NAND has faced reduced endurance. 20nm NAND is down to 3,000 P/E Cycles, and future planar NAND shrinks will continue to reduce endurance.
Data is stored in NAND flash as bits, and these bits are represented by an electrical charge stored in each cell. The ability to store more bits per cell adds capacity to the NAND; in turn, reducing manufacturing costs, and allowing more flash in a single package. SLC stores one bit per cell, MLC increases density by storing 2-bits per cell, and 3-bit NAND stores 3-bits per cell.
SLC NAND requires two voltage states per cell, MLC utilizes four voltage states, and 3-bit NAND stores up to eight different voltage states per cell. Fewer electrons per cell, due to smaller lithographies, increases the difficulty of determining the charge state of each cell quickly and accurately. As a result, each new generation of planar NAND has suffered from lower data integrity and increased error rates.
Another hurdle for planar NAND is the close proximity to other cells as it shrinks below 20nm. Placing smaller transistors closer together creates cell-to-cell interference, resulting in an increasing error rate. This 'noisy neighbor' syndrome increases the bit error rate of NAND, necessitating stronger Error Correction Code (ECC) to combat data corruption. The inevitability of higher error rates are a significant challenge facing planar NAND as it shrinks.
Additional methods are being utilized to deal with increasing error rates, such as DSP. BCH ECC requires the use of more bits in the error correction scheme, and increasingly complex algorithms can result in controller overhead. These challenges have led to a movement to LDPC (Low-Density Parity-Check), an efficient and adaptive algorithm that provides intelligent error correction with less overhead. LDPC utilizes less data for ECC purposes, and can adaptively increase the level of ECC as NAND ages or generates more errors.
Tooling and equipment costs rise as lithographies shrink. At the same time, the amount of engineering and R&D investments required to mitigate scaling challenges are increasing with each successive NAND shrink. This runs counter to the established philosophy of reducing costs through process shrinks. There isn't much debate about planar NAND approaching its scaling limits; the only question is at what point it ceases to be an economically viable approach to increasing density and lowering cost.
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- Page 1 [Introduction: The V-NAND Paradigm Shift]
- Page 2 [Scaling Challenges of Planar (2D) NAND]
- Page 3 [An Innovative Solution: 3D V-NAND]
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