The Cores in Detail
From left to right we have the Northwood, in the middle the Gallatin and finally the Prescott.
First off we will focus on the Northwood or now as its known, the Pentium 4C or P4C. This has been the most successful core for Intel. It arrived directly after the original Pentium 4 flagship, the Willamette core. While only two major changes preceded the design, it certainly turned heads with performance figures, as well as those of overclockers.
The Willamette core used the original 0.18um process for its die. This of course meant that the CPU ran quite hot, and was limited to about or around 2.2GHz and 2.4GHz with extreme overclockers. The Northwood brought with it a die reduction in the order of 0.13um. This was the first CPU ever to use the 0.13um process, and did it change the Pentium 4 forever. With a simple 2.4GHz CPU, speeds of 3GHz were now capable, making it a much more attractive overclocking candidate.
Second on the list was the cache. Despite requests for a larger data cache than 8Kbyte, Intel kept the same L1 data and T-Cache systems but simply upped the Level 2 cache from 256KB to 512KB, making its L2 cache size the largest out of the AMD/Intel war. This itself allowed the Northwood to store twice as much data in its cache buffer, reducing the amount of access needed on the DRAM, in tern allowing for a much better hit/miss ratio.
Apart from this, the design didn't change much, the same Socket 478 was used, the chip looked identical to the Willamette and the same ALU/FPU and instruction sets were used.
The Gallatin or better known as the Pentium 4 Extreme Edition (or P4EE) is actually a derivative of the Xeon processor. The Xeon as most people know is simply a Pentium 4 processor with Dual or Quad CPU support and a Level 3 cache added to further speed up the processor for heavy server tasks.
Intel, afraid of the AMD Athlon 64 CPU, took its Xeon and increased the FSB from 533MHz up to 800MHz, removed the SMP registers and packed it into a 478 pin package. This gave the P4EE a L1 and L2 cache system identical to the Northwood but added a L3 cache of 2MB. With this, Intel hoped to bring in enthusiast PC users who wanted the power of a server CPU in a single package and to also flight off AMD who were set to launch Athlon 64.
Prescott has been the long awaited core upgrade since the Northwood started pushing 3GHz. Prescott, being a 478 CPU looks no different on the top compared to its Northwood of Gallatin brothers, but its under the hood where some changes have actually taken place.
Prescott has moved from the 0.13um process that served the Northwood and Gallatin so well and has gone to the next step up (or down) however you want to look at it. TSMC's latest 0.09um process has been adopted as the die of choice for the Prescott core. This has in tern allowed Intel to increase cache sizes, lower operation voltages and squeeze more transistors on per die than the Northwood is capable of doing.
Secondly we have the cache system. It has finally happened. Intel has moved its L1 data size up a level, as the masses have requested for some time. While a T-Cache increase would have been better for the prefetcher unit, data cache will have to do. Northwood and Gallatin as well as Willamette used an 8KB L1 data and 12Kuops T cache. Prescott has increased the L1 data cache from 8KB to 16KB, in fact doubling the amount of data the processor can store in the L1 buffer.
Along with this, Intel has also increased the L2 cache and removed the L3 cache the Gallatin possessed. L2 cache has gone from 512KB to 1MB, again a 50% increase in cache.
Lastly the biggest addition is Intel's new Streaming SIMD Extensions 3 or SSE3 as it's known. Though it took some time for software developers to realise it, SSE2 was simply a giant leap forward in Multimedia Extension sets, with 144 instructions to use, Pentium 4 processors were simply able to have a much higher FPU power than the Athlon CPU was capable of. With this in mind, Intel has once again thrown the software developers another bone to chew on. The SSE3 instruction set adds 13 brand new instruction to the mix for much more vibrant 3D and mathematical decoding problems that modern CPU come across today.
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