Indilinx Everest 2 Platform - Flash Management
The Everest 2 controller technologically surpasses all other SSD controllers in the industry through an advanced feature set that includes:
Broadest NAND flash support, including 1xnm and TLC
Up to 8 NAND flash channels with up to 16-way interleaving per channel
Up to 535 MB/s transfer rates when using synchronous flash
HyperQueueing and Native Command Queuing (NCQ), with a queue depth up to 32 commands, and algorithms to optimize the order in which read and write operations are executed
Up to 8Gb (1GB) of 800MHz DDR2/DDR3 DRAM cache support
Multi-Level ECC with 128-bit correction capability per 1KB of data
RNA Redundant NAND to protect against catastrophic NAND flash failure
True end-to-end data path protection performs data integrity checks at every juncture where data is transmitted, received, processed and stored to ensure that corrupted data will be detected and not propagated
Power fail protection and optional Supercap support prevents data loss in the event of a power failure
Auto encryption and AES-256 encryption to protect and secure data
Additional flash management techniques such as TRIM, background garbage collection, dynamic and static wear-leveling and advanced flash defect management
Extending the life of NAND flash memory for MLC-based SSD requires a highly intelligent controller that can analyze and dynamically adapt to increasing NAND vulnerabilities as the flash cells wear or process geometries get smaller. The Everest 2 controller, featuring Indilinx Ndurance 2.0 technology, is designed to radically extend NAND flash memory life while providing enterprise-class endurance even when commodity-grade NAND flash is used. Ndurance 2.0 technology suite includes the following capabilities:
Advanced Multi-Level ECC: The advanced, multi-level BCH ECC engine with progressive error correction adapts to the specific error characteristics of different NAND devices. The programmable ECC engine achieves an effective correction power of up to 128 bits per 1KB of data while significantly reducing the uncorrectable bit error rate (UBER).
Adaptive Program and Read Algorithms: Proprietary and vendor-specific program and read algorithms are applied, ranging from internal voltage shifting to sophisticated signal processing techniques that minimize NAND flash deterioration, reduce disturbances that affect adjacent flash cells, and improve data recovery.
Redundant NAND (RNA) Technology: This option safeguards against catastrophic NAND flash failures and uncorrectable data errors by generating parity data information and striping it across multiple NAND flash cells. RNA provides RAID-like protection that enables data to be divided and replicated amongst multiple NAND flash devices within an Indilinx SSD.
Reduced Write Amplification without Compression: Lower write amplification is achieved by concatenating multiple write requests from the host while minimizing wasteful copy back operations of unaffected data sectors. This approach virtually eliminates excessive programming and read operations while preserving precious program/erase cycles without the need for performance-degrading data compression.
As you can tell all of that is from the press release. There are a few key points that I would like to touch on. The first is the longevity of Everest 2. At CES OCZ talked about this platform scaling up to 2TB in user capacity. In this press kit, Indilinx brings up 1Xnm and TLC flash. We should start seeing 20nm IMFT flash used in consumer SSDs in Q4 of this year or Q1 in 2013. That means Everest 2 will be around for the remainder of this IMFT product cycle, all of the next product cycle and into at least the beginning of the one after that.
We've read several stories recently about the current and future struggles flash manufactures face as they progress through shrinking of the technology. In order to maintain a drive that will last at least the length of the warranty period, next generation SSD controllers and their programming need to use advanced feature to conserve the flash. The bruit force methods of the past with high rates of write amplification in order to maintain high speeds will not work in the future.