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AMD Socket AM3 Arrives - The Real Phenom II Detailed - Phenom II AM3 Architecture

AMD today unveils what we like to call the 'real' Phenom II processor with more updates and a new AM3 socket. Read on as we explain what's new.

| AMD CPUs & APUs in CPUs, Chipsets & SoCs | Posted: Feb 8, 2009 5:00 am

AMD's new Phenom II AM3 Explained

 

AMD has definitely scored what we would call a win for the ages as far as its design and compatibility are concerned. But before we head into this, let's just take a little bit of a history lesson. K8 has certainly matured well, but this has caused some compatibility issues. The first issues had arisen when K8 Hammer came out with Socket 754 and supported a single channel memory controller on the CPU. While this platform had great potential, it still wasn't fast enough for AMD or the retail market wanting dual channel DDR memory on the CPU. This was soon after accomplished; however, an extra set of pins had to be added because the extra memory channel was on the CPU, so the pin count jumped from 754 to 939.

 

AMD Socket AM3 Arrives - The Real Phenom II Detailed

 

Now, the big question was what would happen to 754? - Well, it turned out AMD kept this socket for its value CPU Sempron line and still made single channel Athlon 64 processors as well, proving that they would continue to keep this socket right the way through the 939 processors lifespan.

 

When it came time to introduce DDR2 on the AMD K8, a new socket was introduced once again, this being the AM2 (or 940-pin) package array. However, overnight AMD dumped the 939 processors and focused on the 940; it was impossible to get any new 939 processors from AMD after the AM2 was released, which caused quite a bit of a stir for many people, especially amongst those who had just bought a 939 CPU hoping for some upgradability.

 

Dual Mode Memory Controller

 

AMD Socket AM3 Arrives - The Real Phenom II Detailed

 

To start things off on our AM3 processor, AMD has revolutionised the latest addition to the Phenom II family. All of the 800 series and 700 series CPU's have a dual mode memory controller. That is, it has a DDR2 and DDR3 memory controller onboard. This is the first CPU to incorporate two memory controllers on one CPU die.

 

AMD has used the same memory controller that exists in the current AM2 Phenom II processors with a maximum rated speed of 1066MHz. This allows the CPU to be inserted into AM2+ motherboards to run off up to four DDR2 memory slots, which is another plus for AMD as they have not limited the CPU to only two DDR2 memory slots on AM2+ boards.

 

The second memory controller is a dual channel DDR3 interface which supports four DDR3 DIMMs at the JEDEC spec of 1333MHz. There is no information on whether or not it has any XMP or EPP profiles for the modules; however, this is the first DDR3 memory controller from AMD, so we won't go too hard on them just yet.

 

Both controllers support the unganged memory mode which runs two independent 64-bit channels so that you can use mismatched memory modules (different sizes) yet still gain speeds faster than what single channel mode can deliver.

 

Cache

 

The first generation of Phenom II processors only came in one L3 cache size; 6MB. With the new 800 series AMD has also introduced a 4MB L2 cache series. The Phenom II 700 series will retain the 6MB L3 cache since AMD is limiting its cores to a tri-core CPU (X3 series). However, AMD wants to keep a performance gap between the 800 and 900 series, so the L3 cache will be reduced from the 6MB that the 900 series receives to 4MB on the 800 series.

 

In order to help reduce overall power consumption by the CPU, AMD has included a new HLT state. What this does is the Clock-to-Idle sub-cache bus can be periodically stopped to help reduce power consumption. This happens in Windows when the CPU enters the Cool'n'Quiet phase; L3 cache is cut off, allowing the CPU to run even more power efficient than previous generation AMD processors.

 

One of the new features added to the Phenom II series of CPU is Smart Cache. What this does is when the CPU enters its power down state, before access to the L3 cache is cut its Clock-to-Idle sub-cache bus is powered down. The L2 cache memory is then dumped into the L3 cache. This allows the L2 cache to shut down and save even more power. When it's required again, the data from L3 cache can be loaded back to L2 cache for quicker access.

 

Fabrication Process

 

It has taken AMD some time to move its process along, but it's finally happened. 65nm based K8 and K10's have been out for quite a while and in fact the entire AM2 series have been based on the 65nm process. While this is good, by today's standards it's a bit too big and inefficient. Intel has had 45nm products out for over a year with the Penryn based Core 2 and the Core i7. The upcoming Core i5 will also be based on this same 45nm wafer.

 

And finally AMD join them by embracing 45nm technology with the Phenom II processors. The X4 variant's die measures a mere 258mm2 and a total transistor count of around 758 million. That's a lot packed into one CPU. So far the Dresden plant in Germany is the only AMD fab producing the 45nm DLS Silicon on Insulator (SOI) technology, but hopefully AMD will soon have its other fabs producing the wafers to avoid any shortage of processors.

 

The AM3 Phenom II processor is part of the Stars architecture that AMD has called the K10 and is in fact given full support for AMD's Dragon platform. This means that AMD Phenom II 700, 800 or 900 series CPUs when paired with a 790FX/GX chipset board and a HD 4000 series GPU will be part of AMD's Dragon platform design and be awarded the Dragon logo.

 

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