Power Management – The Big Green Giant Goes Even Greener
The biggest feature-set that AMD has worked up in the K10 architecture deals with power management. With the big push to go green in computing, saving power needs to be a high priority these days, and AMD has really gone all out on K10. To do this, AMD has gone on a three-stage setup. The first on the list is Independent Dynamic Core Technology. Depending on the amount of CPU strain the system is under, the K10 is able to run each of the four cores on X4’s and three cores on X3’s at separate clock speeds and separate voltages per core.
Corecool Technology allows the power management system to shut down inactive sections of each core that are not in use. If the memory controller is idle it enters a lower power state; if it’s doing read requests, the write system is shut down, and vice versa.
Lastly is the Split Plane or as it’s now known by AMD as Dual Dynamic Power Management. On previous AMD K8 processors, the CPU is fed one voltage, and this is what is used to run the memory controller built into the CPU; thus if the CPU voltage is increased, the memory voltage also goes up. If the CPU voltage is reduced, the memory controller voltage also drops. This in turn can be a bit of a pain, especially when you want to run the CPU in low power mode. The memory controller may not like the lack of power and could begin to produce data errors. With the new Split Plane design, the memory controller on the CPU is fed an independent voltage supply to the core, allowing the CPU to lower its core voltage dramatically while keeping the memory controller working at full speed.
Hyper Transport 3.0
AMD’s original idea of a unified transport protocol has really made head way. Not only is NVIDIA using it to connect its SPP and MCP’s on both AMD and Intel boards, but AMD uses it for the Integrated CPU Northbridge to external Northbridge communication, and now it’s time for AMD to up the stakes. HT1.x has been around since K8 first came out on the Socket 754 platform, and while it has served well, higher transfer rates are called for now. HT3.0 allows for a total of 10.4GB/s transfer between the CPU and the external Northbridge, where HT1.x allowed only 4GB/s. HT3.0 is also part of AMD’s power saving design as the CPU controller is able to adjust the speed width of the protocol on the fly. If the CPU is not using all of the bandwidth, it can on the fly lower speeds and voltages to save even more power.
True Quad Core Design
This has been AMD’s big claim to fame in that AMD has a true quad core design. Intel has had what they have called the Quad Core series with Core 2 Quad and Core 2 Extreme QX series. While they do contain four cores, they are technically a multi-core arrangement. A Core 2 Quad core CPU has two Conroe Core 2 Duo dies on a single package. Core 1 and 2 communicate across the L2 cache and Core 3 and 4 likewise. However, if Core 1 wants to find out what Core 3 or 4 is doing (or vice versa), it has to send a request along the FSB and back to memory which then goes back to the first die. In a technical sense, it’s as if you have a dual CPU setup running two Core 2 Duo processors.
AMD however has integrated four cores into a single package that access each other across a single system request bus; this bus is the communication point between the CPU cores, the memory controller and L3 cache memory. This allows for a faster core to core communication. This has led to quite a few issues though, that being that if one of the cores comes out of the production line inoperative, this renders the entire CPU useless unless it is able to be disabled and setup as a Phenom X3 processor. Another problem with this design is it limits the amount of speed the CPU is able to be clocked at. So far AMD has only released the Phenom at a maximum speed of 2.5GHz, where Intel has managed to get Quad Core CPUs to 3 GHz and beyond.
